Research Of FPGA Project Module Partition And Relationship Based On VHDL

Human tirelessly for space and outer space exploration promote the rapid development of space and satellite technology. Work in the space of onboard system will be bombarded by cosmic rays of charged particles, make the integrated circuit produce transient fault, namely single event upset. It not only causes the memory content flip, but also affects the normal work of the whole system. In order to consider the reliability of electronic systems and the cost of applying protective measures comprehensively, the FPGA project is divided into several functional modules according to the circuit function. Through the research of each functional module respectively, reliable performance and cost model to take into account the overall under the premise of reliable performance and cost, find the best collection of protective measures.This paper introduces a software system which C language analysis VHDL language. The software system called VHDL function module partition system. The software system can automatically analyzes FPGA project based on VHDL language about function module partition and module topology analysis. The hierarchical design based on VHDL language to achieve the division of function modules of the FPGA project. The FPGA project focuses on the optimization design of the smaller functional module, thus to improve the work efficiency and guarantee the purpose of the electronic system’s high reliability. This paper introduces the hierarchical design method and VHDL language knowledge in hierarchical design, explains the system of VHDL function module partition related important concepts and the overall structure.VHDL function module partition system includes two parts:function module partition part and module topology relationship analysis part. Function module partition part expounds the function module division criterion, which based on this criterion to divide the functional module. Module topological relationship analysis part mainly expounds the specific methods of the top-level file module relationship analysis, illustrates the relationship between child function module relationship analysis and the top-level file module relationship analysis of similarities and differences. The following specific content is about function module partition part and module topology relationship part.Function module partition analysis consists of three parts:the top-level file function module analysis, package function module analysis and child function module division. Mainly task is to scan input file on top of VHDL and grammar rules based on VHDL in VHDL engineering structures in accordance with the keywords to identify the function module, then save the function module to a file. At the same time this part identifies related packages and child function module, in order to find the package and the function module, the declaration of a component is hierarchically divided into each layer of the function module save to a file.Module topological relationship analysis module mainly includes two parts:the top-level file module relationship analysis and child relationship analysis function module. Main content for the top-level file function module is analyzed, and find the top element of the functional modules, through the analysis of element instantiated and element declaration, and find the topological relationship between modules. Pair and functional module is analyzed, and through the child function module components instantiated and components of declarative statements, and identify the topology relationship of each module of function module, the module topological relations in the adjacency list, and then to prescriptive code in the generated file.Finally, a practical FPGA project based on VHDL language is analysiszed. Through software results and engineering actual situation, the measured results show the feasibility and effectiveness of the software system.