Fpga-mcs-51 Core-based Vhdl Language With The Realization

Based embedded microprocessor research, this thesis has independently designed a microprocessor system which can run MCS-51 instructions. The design is described by VHDL and block diagram. All of the instructions has been test successfully on the platform of FPGA . The thesis carefully researches on the set of instructions and data-address access ,and completes the design and realization of fetching instruction unit, instruction decoder unit, memory unit and ALU unit by hardware description language. The thesis researches on the realization method of control unit and the design theory based on overall state machine. Through Principle Map and sample code demonstration, the thesis introduces the instruction decoder of ways. Based on this approach to the formation of decoding circuit also be able to achieve more complex CISC instructions.By means of sub-module design, the system migration is improved greatly by concentrating the same functional logic circuit to on one functional module. System also uses the design means of level block diagram and concentrates the primary and secondary circuit to different levels. This has made the system functional modules can be expanded greatly enhanced. Internal logic consists of data storage module, Program storage module, Timing Control module, Special function Registers module and Core Module. The thesis introduces each module for the design of the details. At the end of this paper, we introduced the result of logic simulation test to some typical instructions. Test results show that the MCU system can work normally. AS expected, the values of corresponding registers and bus meet design requirements, and this system achieves design goals.