Development Of FPGA Internal Function Module And Module Control IP Core For Small PLC

Based on the previous projects of the research group,this topic mainly studies the FPGA internal control module of the small PLC,the logic operation module instruction execution process and the stack operation programming method,and optimizes the timer circuit structure and the instruction encoding format.Designed with the ARM and FPGA system as the host of the new PLC developed,the advantages of high-speed parallel processing of FPGA are fully utilized,and the data is exchanged on both sides through the dual-port RAM.In turn,the functions of logic operation,timing and counting of PLC instructions are completed.And after the instruction ends,the instruction operation result data is sent to the ARM side.Mainly achieved the following results:(1)The characteristics of reading and writing of each storage space of dual-port RAM are analyzed,and the methods and design principles for avoiding the occurrence of read-write conflicts are proposed.According to the basic composition of FPGA module,the processing workflow of FPGA module is designed.The FPGA internal control module is designed,and the interface circuit between FPGA and ARM is designed to realize the communication between the ARM side and the FPGA side.In addition,this study has planned and divided the storage area of the dual-port RAM between FPGA and ARM.The instructions transmitted on both sides have been modified to optimize the timing of the FPGA control of each functional module.(2)For the FPGA logic operation module,the ladder program module is divided,the basic principle of the stack operation is proposed,and the stack operation and execution process of the instruction executed by the logic operation module are standardized,thereby perfecting the design scheme and determining the instruction execution.The process and stack operation programming method,planning and designing the timing.Redesigned and modified some of the instruction formats to complete the encapsulation of the IP core and the debugging of the logic operation module.(3)For the timer module,the design idea is put forward,and the internal bus of the timer module is designed.The three modules of the 1ms,10 m and 100 ms timers are connected to the timer input and output control port module through the bus,and the timing overflow of the timer is proposed.The processing method realizes the function of the FPGA-based internal timer of the FPGA.And the encoding format of the timer instruction is optimized,and the encapsulation of the timer module is completed.(4)The design of the counter module is completed.The working principle of the counter module,the characteristics of the counting signal,and the processing method that the counting value has reached the counting value are analyzed,and the function of the counter module is realized.And the encoding format of the counter instruction is optimized,and the encapsulation of the counter module is completed.(5)Simulation verification is performed for the logic operation module,timer module and counter module after the design is completed.Write the testbench simulation test file to observe the simulation waveform in modelsim software,and finally download the simulation-free program to the development board for board-level verification,and the test result is correct.