Design And Implementation Of The PD Radar Digital Signal Processor Based On Zedboard

Radar signal processor is the core component of a radar system, which directly affects the performance of radar. The continuous development of modern combat weapon stealth technology and the increasingly harsh environment of the battlefield are more and more demanding, not only for its detection ability, but also the requirements of the radar in a high processing accuracy, strong anti-interference ability and high reliability, with a small volume and weight, in order to facilitate the use of various mobile platforms. Digital radar signal processor is the trend of the times thanks to the inherent advantages of digital circuit in accuracy and reliability. However, special radar digital signal processing chips have little demand compared with consumer grade digital chips. This result in the digital radar signal processing chip designed with ASIC method has disadvantages of high production cost,low flexibility and extendibility. Besides, common implementation method of FPGA+multi DSP is also facing the problem of large volume, high power consumption and inconvenient maintenance.Parameters configurable PD radar digital signal processor is desined and implemented based on Zedboard which improve the flexibility and applicability The processor has real-time configurable features with the following parameters: pulse compression processing point from 32 to 4096, the number of PRT in a CPI from 8 to 256. The processor can realize digital down conversion?DDC?, pulse compression?PC?, moving target detection?MTD? and constant false alarm?CFAR? processing. The DDC module, PC module, DDC module and MTD module are implemented based on FPGA hardware, and CFAR processing is implemented based on software algorithm.First, processing flow of PD radar digital signal processing is introduced and related theories and algorithms are analyzed.The DDC module is designed and implemented by combination multi phase filtering structure and multi channel filter structure. Mixing, 8times extraction and filtering are done based on a single clock frequency module.Configurable pulse compression processing with variable-points from 32 to 4096 is implemented based on pipelined FFT processing module which designed by radix-2algorithm and SDF architecture. The depth selectable asynchronous FIFO module is designed to realize the data acceleration between DDC and PC module which improve the overall performance of the design and radar digital signal can be processed in real time.In addition,overall design and simulation and verification of key submodule are completed with Matlab software algorithm model as reference.takes the Matlab software algorithm model as the reference, and completes the design and the key submodule simulation and verification. Finally, the PD radar digital signal processor is implemented based on the Zedboard platform. The results of the actual design are compared with the results of Matlab software and the relative error is analyzed. Board level verification results show that the maximum operating speed of the DDC module can reach 320 Mhz which relative error is 10^-4 and the maximum speed of PC module is 240 Mhz which relative error is10^-4.The whole function of radar signal processor is correct and the maximum speed is240 Mhz which relative error is 10^-4.