System Design And Development Of Missile-borne Radar Signal Processor

With the theme of designing and developing a signal processor for a millimeter wave radar seeker, this paper introduces the design of the signal processor hardware platform and the system design and algorithm implementation in FPGA in the order of design thought and development process.This paper begins with the introduction of the operation modes and transmitting waveforms of the radar seeker. The operation modes include pulse Doppler and stepped frequency. Because of the large Doppler shift caused by a minor speed of the target when the radar seeker works in millimeter wave band, the pulse Doppler mode is adopted for the moving target. As for slow-speed or stationary targets, the stepped frequency mode is adopted. By synthesizing multiple pulses, the high resolution range profile of the target scene can be obtained which facilitates the target detection and recognition. The transmitting waveforms of the radar seeker include simple pulse and linear frequency pulse, the first one for near targets and the other for distant targets. Thus the operating range of the radar seeker is effectively improved.The signal processor hardware platform applies a FPGA+DSP system architecture, in which a low-power, high-performance FPGA of the Xilinx Kintex-7's latest series is selected as the main signal processor and undertakes most of the signal processing tasks, while a low-power DSP is selected as the auxiliary processor. The algorithm development in this paper focuses on the FPGA and commences with the task division which defines the functions and tasks undertook by the FPGA in different operation modes. The radar seeker has multiple operation modes and transmitting waveforms, which requires that the algorithm in FPGA should be reconfigured. Due to the application of a unique system control code to adjust the functions of the internal modules and to change the direction of data flow, FPGA is able to adjust its signal processing procedure depending on the operation mode and the transmitting waveform to complete signal processing tasks. Followed by the top design of FPGA is the introduction of the principles and FPGA implementations of the main signal processing algorithms in different operation modes. These signal processing algorithms include digital down converter (DDC), pulse compression, moving target detection (MTD), spelling range profile, cell average-constant false alarm rate (CA-CFAR).Finally, according to the existing conditions, this paper proposes a test and verification scheme for FPGA, which divides the algorithms and functions into the front part and the back part and verifies them separately. Through the theoretical simulation, the function simulation and the hardware verification of the front part and the back part, the functions of FPGA are ultimately verified.