Design And Study On Configurable FFT Processor With Low Memory Requirement For High Resolution Applications

Discrete Fourier Transform (DFT) and its simplified algorithm Fast Fourier Transforms (FFT) play important roles in digital signal processing fields. FFT processors have already been widely used in communication systems, image processing and radar imaging systems. Recently as the communication technology advances and VLSI design productivity improves, new applications, such as high resolution radar and DVB-T, came into use. Consequently the FFT resolution has been greatly risen to 2048, 4096, even above 8192. Some standards like DVB-T and WiMAX also support multi-point FFT. The new requirements have been assigned to FFT processor designers.In this thesis, according to these newly appeared challenges, a method of designing high speed, configurable, high precision, and low storage FFT processor is presented. The main contributions are listed as follows: 1st, improved radix23 algorithm is presented. The processor pipeline now support 2n points transform via configurable data path and use less multipliers as well. 2nd, Analyzed finite word length effect and introduced custom float format to the pipeline to improve memory utilization. Now the memory usage is 11% less then fixed FFT processors, also with precision improved.At last we vrifyied the processor's function with PLI based RTL/C++ mixed verification methodology. The FFT processor is implemented on a Xilinx chip XC4VLX25- FF668-10C, consuming 90kb embedded RAM with 10 bit input data, and obtains the operating clock frequency at 100MHz.The processor can compute a complex 1024-point FFT within 10us and 4096-point FFT within 40.1us.