Configurable Processor Based On Advanced SOC Design Methodology

In order to meet the challenges faced by IC design industry, advanced SoC design methodology was proposed with the idea of evolving the design approaches from“hard-wired logic centric”to be“processor centric”. As the result of widely used configurable processors inside, future SoCs can be highly flexible, which helps to enormously improve the R&D efficiency throughout the design, verification and maintaining stages.As the basic component of SoCs, configurable processor is a key technology in the framework of the design methodology. Probing into this point, the article presents a configurable, extensible and“interface flexible”processor architecture, including a baseline architecture that is highly-integrated and“ready for extension”, as well as an extension architecture that is specifically strengthened for audio computation.According to experimental results, the proposed architecture is predominant in performance and cost, when compared to state-of-the-art solutions.The proposed baseline architecture employs an improved instruction field allocation strategy to reach a balance of performance, complexity and flexibility. Its synthesizable soft-core is superior to the existing processor IPs in timing and area characteristics (with the maximum frequency over 120MHz and minimum area of 866 LUTs on Virtex IV FPGA).The proposed audio extension architecture is strengthened via the technologies of data flow model, instruction concurrency, memory parallelism, flexible addressing, post-processing and zero-overhead loop, on the basis of preserving all the merits of RISC pipeline. Performance analysis shows that the audio algorithms (such as FFT) running on this architecture, is 6 times and 5 times as fast as on ARM9E and ARC600 (with DSP enhancement), respectively.