Design And Implement A Configurable Processor For AES Encryption

With the rapid development and wide application of computer technologies and network technology, information security gradually becomes an interesting subject. National Institute of Standards and Technology announced Advanced Encryption Standard(AES) as data Encryption Standard, which has certain advantages over original symmetric encipherment algorithm in security, conciseness, cost, and have widespread application prospect. Traditionally, AES was implemented based on the DSP or ASIC. This paper states a method of implementation based on the Transport Trigger Architecture(TTA) configurable processor. To some extent, this method makes the compromise between performance and flexibility.Firstly, this paper describes the architecure, hardware and instruction set system of TTA configurable processor. Afterwards, AES algorithm is analyzed and implemented by c language. According to statistic on C*Core C310, Byte Multiplication is transformed to looking up table. Secondly, parallel optimization methods of AES algorithm based on TTA and very long word is discussed, which are parallel implementation of Key Expansion and Round, simplifying dataflow of Round, customizing function unit and instruction set according to special operation. Automation is one of the most difficulties of configurable processor design, and necessary condition of widespread use of configurable processor. This paper lays stress on auto-generation method of RTL code and configurable assembler based on TTA. RTL code and assembler of special instruction set for AES encryption was auto-generated by RTL auto-generation software and assembler. Finally, results from software and FPGA verification show that for 128-bit plaintext, 128-bit cipher key AES encryption, the throughput is 18Mbps, which is better than general processors and DSP. Because of auto-generation technique, it is shorter and easier than that in ASIC. Because encryption algorithm is implemented by software, it can against attack, but there is certain gap with speed that in ASIC. Thereby research space is so much in this area.