Design Of Digital ASIC In High Precision Sigma-delta DAC

The digitalization of MEMS gyroscope is one of the focuses in the field of inertial sensor systems,and the digital MEMS gyroscope system has gradually become the mainstream of design.High precision DAC is one of the key modules in the digital MEMS gyroscope system.The purpose of this thesis is to design a high precision sigma-delta DAC digital front-end integrated circuit(ASIC)used in MEMS gyroscope.The main contents of this paper include three main modules: digital interpolation filter,sigma-delta modulator and DEM dynamic matching module.The cascade multilevel digital filter design using digital interpolation filter structure,cascade structure including two half band filter,CIC compensation filter and CIC filter,based on the analysis of the traditional half band filter,a robust half band filter structure is proposed,the structure of traditional half band filter transfer function was improved,the amplitude frequency characteristics of the sensitive degree of filter coefficient is lower,and the structure has the characteristics of low consumption of hardware circuit,high circuit speed and lower power consumption;in order to realize the digital front-end ASIC high precision digital stream out,this paper introduced a design of digital sigma-delta modulator with multibit quantization cascade structure.The structure of error feedback is adopted in this design,and the high-precision ASIC digital bit stream output is realized through multistage cascade,so as to reduce the loss;Considering the multibit digital quantization technique of modulator is easy to produce nonlinear problems,this paper designs the dynamic matching unit,using digital weighted average algorithm(DWA)to produce the output signal of the modulator mismatch noise into white noise then filtered by low-pass filter.In the implementation of Sigma-Delta DAC digital front-end ASIC structure,a variety of technical optimization has been carried out.Firstly,the structure of digital interpolation filter is optimized based on the sample and hold circuit,in order to further reduce the power consumption,the design of interpolation filter structure is designed;in the aspect of hardware circuit structure design of multilevel quantization digital sigma-delta modulator,using a MASH1-1-1 structure,each a quantizer with downwards truncation to achieve the multiplication operation by using displacement mode,to reduce the circuit area consumption;the algorithm is implemented in DWA hardware structure,based on the thermometer code,using cyclic shift way;in order to reduce the number of input data port,the serial bus SPI interface is used to convert the parallel input data into series data.Finally,I achieve the hardware implementation of the whole digital front-end ASIC,using Cadence company's Encounter software,then making layout based on 0.35 ?m CMOS technique and do the timing optimization,the overall layout of the physical simulation,and implemented the design,the chip area is 3.0mm×2.8mm by FPGA the design of the whole circuit is tested.The experimental results show that the signal-to-noise ratio of this digital front-end ASIC is more than 143.5dB,and the effective bit is about 23.5 bits.