| For its facilitate the mobile storage devices are widely used in recent years.The ways to protect the stored data are software encryption and hardware encryption.Hardware encryption have a lot of advantage and got more and more attention,and the hardware implementation of cryptographic algorithms are the key of this one.With the development of cryptography,AES has been widely used in industrial and commercial fields.There are two ways to achieve AES in hardware,ASIC and FPGA.Currently the AES algorithm implementation with the ASIC has been able to achieve 51.2Gbps.FPGA development platform to implement cryptographic algorithms is more flexibility than use ASIC.This paper using DE2-70development platform, achieve AES encryption algorithm in the mode of 128-bit initial key with 128-bit plaintext data in Altera’s CycloneII FPGA chip named EP2C70. In the AES algorithm it will use pipelines technology and implement key expansion algorithm in non-symmetric mode, to improve the algorithm execution throughput. Encrypted data will be stored in a NOR Flash chip. Using LCD to display cipher text to prove the logical correctness of the algorithm.The AES hardware encryption and data bit transformation circuit and Flash chip controller are written by the Verilog language, the compiler environment is QuartusII 9.0. After tested, the design of the AES algorithm module is correct, it can encrypt and decrypt data and the display the result on the LCD1602. It also can encrypt 16-bit wide data and store result in the flash memory. |