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AES Encryption Algorithm For FPGA Implementation

Posted on:2012-12-23Degree:MasterType:Thesis
Country:ChinaCandidate:K E HuangFull Text:PDF
GTID:2218330371952357Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
Data encryption system develop with human security for the information. Encryption algorithms is the core theory of encryption system. Encryption algorithms changed during the past years. Currently , AES (Advanced Encryption Standard) algorithm is widely used in the industry , and it is one of the symmetric encryption algorithms. AES can ensure the safety of nearly 20 years it can not be cracked.There are many ways to achieve encryption system,but hardware implement can get great optimized in performance. It has been widely used in the situation that the encrypted data is large and the real-time requirements are relatively high. Contrast with ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable Gate Array) in implementation complexity and cost, ultimately select to describe the FPGA implementation AES encryption algorithm in this thesis. At the same time simply introduced ASIC implementation process.In this thesis,mainly analysis the structure of AES encryption algorithm. After a detailed analysis and optimization of the algorithm in the re-use of sub-module, make use of the Verilog language to describe the algorithm for hardware implementation. In the hardware implementation process, taking into account to maximize the performance of encryption, the complex module of the algorithm has been optimized separately . It also shows the sub-module for each module schematic and RTL (Register Transfer Level) level integrated structure in the thesis. AES algorithm achieve the ultimate IP core form of fixed interface signal, interface timing, and internal implementation.In order to provide system stability, each hardware module has get verification. At the same time encryption system uses two authentication methods: FPGA platform and the application language of verification platform. Finally, this thesis analyzes the performance of AES algorithm , the occupation of resources and performance bottlenecks, and shows the AES algorithm in FPGA and ASIC on the application implementation.
Keywords/Search Tags:AES, hardware encryption, encryption algorithm, verification
PDF Full Text Request
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