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Its FPGA For The AES Encryption Algorithm

Posted on:2014-04-13Degree:MasterType:Thesis
Country:ChinaCandidate:L WangFull Text:PDF
GTID:2268330398499368Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In todays era of rapid development of information technology, network notonly bring a lot of convenience to our lives, but also contribute to the continuousdevelopment of the field of aerospace, military and business. Therefore, informationsecurity, especially in data storage and transmission of data security is particularlyimportant. Data encryption technology plays a vital role in data security, it is toprotect sensitive information from malicious attacks from the outside world, so thatthe data can not be stolen or tampered, encryption technology has also been a hotresearch on the international topic.The current Data Encryption Standard is AES encryption standard, alsoknown as Rijndael algorithm, which replaces the DES and3DES and become a newgeneration of information security encryption standard in the21st century. Thepaper researched the AES encryption algorithm, get its performance of the algorithmby analyzing its algorithm structure and encryption principle, and design a specificalgorithm optimized for the S-box algorithm to improve the algorithm complexity andsecurity. Selected non-feedback mode which is suitable for hardware implementationand design a mixed internal and external pipeline structure which is efficient and lowresource utilization.Design using the Nios II CPU on SOPC integrated implementations. Whichinclude encryption and decryption functions, configurable key, and resourceutilization and throughput are ideal on FPGA design. Using custom components andmake a reasonable division of the hardware and software to narrow the gap of thehigh-level language and machine instructions so that it can realize the complexityof the AES instructions. System adopts the state machine control to wheel transform,apply internal expansion for encryption and external expansion for decryption toimprove the execution speed of the system. By Modelsim simulation, analysis of theperformance parameters and horizontal comparison system design with otherdesigners, the design reflects the advantage in execution speed and resourceutilization.
Keywords/Search Tags:AES encryption, SOPC integration, mixed internal and externalpipeline structure, FPGA
PDF Full Text Request
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