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Design And Test Of Keeloq Algorithm Encryption And Decryption Circuit Based On FPGA

Posted on:2017-06-06Degree:MasterType:Thesis
Country:ChinaCandidate:S YangFull Text:PDF
GTID:2348330503472414Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The attention of information security is promoting the development of encryption technology and innovation. Keeloq rolling code encryption technology because of the cipher-text are not the same each time you send, and therefore able to withstand electromagnetic intercept attacks, protect the safety of the encryption process, which makes high-reliability encryption algorithm based Keeloq increasingly popular. However, at present the algorithm is mainly in the form of embedded software in microcontroller cured, non-portable, slower to execute.Aiming Keeloq algorithm we designed a encryption and decryption application system based on FPGA and verified the performance of the algorithm on the FPGA. The circuit has a portable, high speed, and high reliability.On the nonlinear function, we use a look-up table manner, thereby reducing the arithmetic logic circuit hardware overhead. Necessary algorithms, the paper auxiliary module is designed to coordinate the implementation of encryption and decryption. To ensure the reliability of the algorithm, we learn the theory of software testing, mainly to the boundary value, equivalence partitioning error derivation, logical overlay, the base path, loop testing, static testing based on seven aspects of the establishment of a more complete test use cases and thus designed the test stimulus.Using Altera CYCLONE IV FPGA family to Keeloq encryption and decryption circuit designs were realized, encryption and decryption circuit consumes 682 logic cells, the highest frequency is 146.26 MHz, which increased by about 7.3 times compared to the previous speed of Keeloq algorithm currently widely used PIC16F88 MCU software implementation. Only changing the 16-bit synchronization value of Cipher-text, the smallest change rate of the test is 34.4% and the maximum rate of change is 59.4% and the average rate of change is 48.1%, which close to the ideal value of 50%. By FPGA verification and related tests show that the algorithm designed Keeloq function correctly, meet the design requirements.
Keywords/Search Tags:Keeloq, Encryption algorithm, FPGA, Software testing
PDF Full Text Request
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