Research On Fault-tolerant Reconfigurable Array And Application

In recent years, along with the rapid development of the integrated circuit design and manufacturing technology, the feature size of the chip decreases sharply, so the number of transistors per unit area can accommodate rapidly increasing, however, at the same time, it also makes the failure probability of the electronic systems increase during their working process, especially in the critical systems of the deep space exploration, aeronautics and astronautics, defense and military, et al. application domains, the poor and complex physical environment requires the circuit systems must have a degree of fault-tolerant capability. Reconfigurable hardware has been used widely as its flexible function. It has important practical value and research significance to design a kind of reconfigurable hardware which could tolerant faults independently.A kind of reconfigurable array is designed, and the fault tolerant methods of the array had been studied in this paper, the main research work is as follows:(1) A kind of coarse-grained reconfigurable array with fault-tolerant capability which adopts network-on-chip router as its interconnection unit to improve the flexibility of the module connection, and a sort of RISC CPU as its computing unit is designed. The computing unit contains arithmetic logic unit and multiply-accumulator these two calculation kernels, it has strong operation ability, suitable for application domains with intensive MAC operation, such as digital signal processing and so on. The fault-tolerant reconfigurable array can be divided into the transport layer which is constituted of network-on-chip and cell layer which is made up of the process units.(2) The system uses triple modular redundancy(TMR), extended hamming code and fault check and retransmission mechanism to tolerant the transient fault of the interconnection wires between the ports in the transport layer. The TMR is mainly used to reinforce the data flow control and link state signals, and extend hamming code can correct single bit fault and detect double bits error in the data, in addition, fault check and retransmission mechanism is used to realize the double bits error correction, these methods can decrease bit error rate effectively. Further more, when the permanent faults occur, the adaptive routing and wire built-in self-test and self-repairing mechanism could be triggered to solve these problem. Mimicking the differentiation of the embryonic cell of the organism, when the cell in the cell layer is failure, the array will be differentiated into various forms by loading different configuration information for each cell during the system initialization stage, so the failure element could be replaced by the normal spare cell in the array to complete the corresponding operations, this ensure the system achieving the original function.(3) A 19 orders audio FIR bandpass filter is mapped into the 3×3 fault-tolerant reconfigurable array, the feasibility and effectiveness of its fundamental computing function and fault-tolerant mechanism is verified.