Research On Self-repairing Reconfigurable Array For Digital Signal Processing

Digital signal processing is the primary method of modern signal processing system, which iswidely used in modern radars, automatic control and instrumentation fields, while for the criticalapplications in harsh environments or some high reliability and security areas, the higherrequirements are needed for high-performance digital signal processing system, which prompting thecombination of fault-tolerant technology and digital signal processing technology. Reconfigurablearray is one of hardware implementations for digital signal processing algorithms, compared to otherhardware implementations, the reconfigurable array has the advantage of distributed reconstruction,this structure characteristic provides more flexible approaches for the design of high reliable digitalsignal processing systems.The self-fault-tolerant method means that the reconfigurable array could realize self-repairwithout the control of external controller. Existing self-fault-tolerant methods in reconfigurable arrayhave difficulty in realizing re-routing and the routing congestion and delay problems are becomingmore serious, especially in the application of large-scale system, which may lead to the poorfault-tolerant ability and large time overhead. To solve the defects of existing reconfigurable arrays,this paper takes the digital signal processing as a specific application object, and presents a novelself-fault-tolerant method of reconfigurable array. The main work of this paper is as follows:(1) On the basis of studying the typical digital signal processing algorithms, general cell unit ofreconfigurable array is designed. The structure of reconstruction in the self-repairing reconfigurablearray is improved by two aspects, which are reconfiguration method and rewiring structure, thepresented reconfiguration method is based on the idea that the configuration memory constructed bythe shift registers, and rewiring structure proposed in the paper is designed by combinational logiccircuits. The new reconfigurable array not only reduces the redundant resource utilization and timeconsumption of reconstruction process.(2) The FIR filter is selected as the verified example, which is the one of most typicalalgorithms of digital signal processing (DSP). Choosing the appropriate FIR filter structure as themapping example to the novel reconfigurable array oriented to DSP, simulated through the software,and the simulation test results have indicated that the availability and self-healing function of thenovel self-repair reconfigurable array oriented to DSP. Finally, by analyzing and comparing with other reconfigurable arrays in fault-tolerant ability, hardware resource overhead and fault-tolerant time, itcan be shown that the method proposed in this paper improves fault-tolerant ability, reduces hardwareresource overhead and time cost..(3)The paper presents the reconfigurable array experiment platform and high-speed ADDAconversion chip, and the FPGA core boards are cascaded to form the structure of the reconfigurablearray experiment platform, which use XC2S200-5pq208c as major control chip. This paperexemplifies the FIR filter, which is downloaded to the FPGA core boards of reconfigurable arrayexperiment platform, to verify the effectiveness of FIR filter and the function of self-fault-tolerancebased on the novel reconfigurable array oriented to DSP with the use of high-speed ADDA conversionchip.