Research And Design Of Fault-tolerant Technology For Network-on-chip Based On 2D-mesh Interconnection

As the design of microprocessors entering into the age of multi-core and many-core system,the communication between the cores has become the bottleneck in performance improvement of processors.While the network-on-chip effectively solves the problem and it has become the mainstream communication architecture of the interconnection between on-chip cores.However,the advance of chip manufacturing technology causes the sharp increase of the chip scale,the chip failure rate is becoming higher and higher,which leads to the result that the research of the network-on-chip reliability becomes one of the most important aspects of the related research of the network-on-chip.What's more,the fault-tolerant ability is an important index to evaluate the reliability of network-on-chip,and it has become the hotspots of the academic research in recent years,while many deficiencies remain to be done.Fault-tolerant router and fault-tolerant routing algorithm are two important parts in the fault-tolerant system of network-on-chip.The project focuses on the two aspects,aiming at solving the shortcomings of the research on the network-on-chip based on 2D-Mesh interconnection,paying more attention to fault-tolerance of FIFO in network-on-chip router,fault-tolerance of ports in router based on virtual channel dynamic allocated,and adaptive fault-tolerant routing algorithm.The main work and the results of the research are reflected in the following three aspects:1?An online detection and fault-tolerant design for FIFO faults in network-on-chip router is proposed.An online testing algorithm for FIFO faults in network-on-chip router is designed based on the function model and fault model established,which can finish the faults testing in the real-time process of the system,and the high coverage of the algorithm is proved through the theoretical analysis.Then,to implement the testing algorithm in the way of hardware,a test circuit for FIFO is proposed,and the corresponding fault-tolerant mechanism is put forward,which forms a complete fault-tolerant system for FIFO faults in the network-on-chip router.The simulation results illustrate that the scheme can effectively complete the fault-tolerance of the router FIFO under the presence of FIFO faults,and the scheme can effectively improve the performance of the network-on-chip when the packet injection rate reaches a certain value through setting the reasonable testing parameters.The synthesize results demonstrate that the hardware overhead of the design is increased by approximately 12% compared with the baseline wormhole router.2?A design of fault-tolerant router whose virtual channel is dynamic allocated based on port fault granularity partition is proposed.The granularity of port fault is partitioned based on the specialty of the port faults,a fault and congestion prediction model for ports based on granularity partition is established by analyzing the characteristics of the virtual channel dynamic allocation combined with the queuing theory.Then,the real-time faults detection module is designed to diagnose the faults,the adjacent port sharing module is designed to tolerate the coarse-grained port faults,fault-tolerant control logic of virtual channel is designed to tolerate the fine-grained port faults,and the fault-tolerant and congestion mitigation scheme is presented.The simulation results illustrate that the port fault-tolerant scheme proposed has good ability of fault-tolerance under various port faults modes,and the synthesize results demonstrate that the scheme has better ratio of performance improvemet and area overhead.3?An efficient congestion-aware adaptive fault-tolerant routing algorithm is proposed.A novel real-time perceptual mechanism for node adjacent 32 links faults is established based on the analysis of the situation that current fault-tolerant routing algorithm lacks the ability to deal with complex fault and congestion status,and a new congestion perception mechanism is proposed by expanding the router delay model.Then,the priority is set for fault handing and congestion handing,the fault processing module and the efficient congestion processing module is designed in the form of logic circuit and the methods of deadlock-free and livelock-free is proposed,which builds a complete set of on-chip fault-tolerant routing algorithm.The simulation results illustrate that the algorithm can maintain the better ability of fault-tolerance and congestion-avoidance under the complex faults mode,the hardware overhead of the algorithm is increased by about 29% compared with baseline wormhole router,and it has the better ratio of performance improvemet and area overhead.