Fault-Tolerant Routing Algorithms For 2D-MESH Based Network-on-Chip

With the unceasing evolution of semiconductor process technology, the needs to the integrated circuit reliability request are also under unceasing enhancement. Traditional routing has simple logic. If something did go wrong, the router could not correct itself and the network could be broken down easily. Fault-tolerant routing plays a key role in the stability and efficiency of on-chip communication. Fault-tolerant routing has very complicated logic, amounts of calculation and processing delay, and also high consumption of energy. As to the large growth of demanding of high-performance System-on-a-Chip, research on fault-tolerant routing is great significant.This thesis analyzes the Networks-on-Chip architecture, fault-tolerance methods and domestic and international research, bring out two improvement ideas. Aiming at the shortage of the current 2D MESH based XY algorithm and DyAD-OE algorithm, this thesis uses their advantage for reference, and tries to prosthesis their disadvantage, puts forward and realizes fault-aware based XY fault-tolerant routing algorithm and improved DyAD-OE routing algorithm.Used NIRGAM simulator, some communication failures in Networks-on-Chip are presented. In this setting, function tests and performance experiments are done to validate algorithms. These experiments show that XY fault-tolerant routing algorithm creates a little additional overhead, and the improved DyAD-OE routing algorithm not only has the ability to fault-tolerant, but also has a greater performance.At last, this thesis constructs a JPEG encoder as a multimedia application, and then maps the tasks into fault Networks-on-Chip modeled with NIRGAM simulator. The validity of the proposed algorithms is verified by simulated fault experiments.