| With the rapid development of semiconductor manufacturing technology, the complexity ofdigital electronic systems greatly increases, and the failure probability also increases during thelifetime of digital electronic systems. Therefore, in some application fields which have strict requestof high reliability, such as aerospace, the fault-tolerant design of digital electronic systems isespecially important. The structure characteristics of reconfigurable circuit provides more flexibleapproaches for the design of high reliable digital electronic systems, however, the existingfault-tolerance design of reconfigurable circuit has low redundancy resources utilization, complexfault-tolerant algorithm, and usually depends on external processor. Therefore, the research ofautonomous fault-tolerant reconfigurable circuit has great importance.This paper mainly researches the structure design and the fault-tolerance approach ofautonomous fault-tolerant reconfigurable circuit, the main research work is as follows:(1) The fault-tolerance approaches of traditional reconfigurable circuit usually depend onexternal control, and most approaches are difficult to realize online, and the redundancy resourcesutilization is low. To solve these problems, this paper designs a hierarchical reconfigurable array,which can realize online autonomous fault-tolerance at array-level. This array is divided intoorganization layer, cell layer and module layer, base on this structure, a hierarchical fault-tolerancemechanism is proposed. Using this mechanism, the array is able to locate fault accurately, and use lesshardware to complete repair. In this reconfigurable array, the function cell design uses the principle ofhot back-up to ensure realization of online fault-tolerance. The fault tolerant control method borrowsthe idea from immune mechanism, and a new kind of cell, named management cell, is designed toperform the testing and repair control. The management cells can test function cell, and chooseappropriate fault-tolerant mechanism by fault diagnosis. The experiment indicates that, thefault-tolerant mechanism of this hierarchical reconfigurable array is flexible, the redundancy resourceutilization rate is relatively high, and the fault-tolerant process does not affect the normal work ofarray.(2) In order to simplify the testing process, reduce the time cost, and improve fault-toleranceability of cells, this paper designs a novel cell with online self-test and self-repair ability, and realizeonline autonomous fault-tolerance at cell level. A cycle self-test method is given to test the logicblocks inside the cells, and a new self-repair method is proposed to deal with the multiple faults of lookup table. The experiment indicates that, the fault-tolerant process is carried out online, the timecost of self-test and self-repair process is relatively low, and the cell’s fault-tolerance ability ispromoted.(3) The application circuit instances are realized function mapping on the reconfigurable circuit,and Modelsim software is used to carry out simulation analysis. Using Xilinx XC2S200-5PQG208CFPGA as core, we design and develop reconfigurable circuit verification board. Then thereconfigurable circuit is downloaded to verification board for testing, and the experiments verify thefeasibility and correctness of the design. |
