The Design Of Resolution Configurable Digital Decimation Filter For Sigma-delta ADC

With the widespread use of integrated circuits, VLSI also toward the high speed, low power in the direction of rapid development. ΣΔADC is the core modules of data conversion and transfer for integrated chip, ΣΔADC also recent research in the design and application of the ΣΔADC prominent exception. Digital decimation filter is an important module of the ΣΔADC. Based on this background, this paper has designed of resolution configurable digital decimation filter for ΣΔADC.ΣΔADC including two modules, ΣΔ modulator and digital decimation filter, so that the theoretical basis of this paper is that analysis modulator and ΣΔADC in-depth. ΣΔADC data conversion have four stages, which is oversampling, noise shaping, decimation and filtering. ΣΔMs completes two tasks of oversampling and noise shaping. And in order to improve the resolution of ΣΔADC, a digital decimation filtering has to complete decimation and filter. Digital filter is generally divided into two kinds of filters, FIR filter and IIR filter. FIR filters and commonly have cascaded integrator-comb filter, compensation filter and half-band filter. Cascaded integrator-comb filter is one of the simplest structure of a filter, which is frequently used for the first stage of a multi-stage digital filter with no multiplier required, a simple structure changing and extraction rate. Due to less demanding conversion accuracy and filtering, so it also uses a cascaded integrator comb filter structure to achieve digital decimation and filtering only in the industrial ΣΔADC. This design uses a single-stage integrator comb filter structure. Due to the design requirements of the parallel data converted value output, a conversion structure is used. And on this basis, it gets 32 to 4096 times lower sampling rate respectively 5 ~ 12 bit resolution by changing the resolution of the down-sampling rate can be configured. In the design part of this paper, the serial output of a single-stage CIC filter and the parallel output filters were compared about the area and power consumption. And because the serial output structure need to add serial-parallel conversion circuit, I used structural transformation after parallel output filter structure.Paper-based reverse engineering, using SMIC 0.18 m 3.3V Mix Signal 1P5 M process for the resolution of configurable digital decimation filter simulation. ΣΔMs output effective resolution is 11.66 bit, and digital decimation filter output effective resolution is 11.55 bit. The highest bit is the sign bit, so it meet the design requirements. At the same time resolution can be configured to achieve low-power circuit design.