The Design Of Low Power Decimation Filter In∑-Δ ADC

This article focuses on decreasing the power of the decimation filter in Σ-Δ ADC.By combining the Noble theorem and polyphase decomposition to improve thesystem architecture, optimizing the structure of the circuit to reduce powerconsumption. Simulation result shows that the power of the digital decimation filterhas decrease nearly50%.Sigma-delta ADC is mainly used in high-resolution data conversion andprecision measurement, etc. It mainly composes two parts: Σ-Δ modulator anddecimation filter. The Σ-Δ modulator has a sample frequency much larger than thesignal’s nyquist bandwidth, and to convert the input into a high-speed low-resolutiondigital signal. In time domain, this digital signal is disciplinary which includes usefulsignal and noise. In the frequency domain, the useful signal and noise are separated.In order to eliminate the noise, the digital filter should be used to filter the noise andkeep the useful signal unchanged. The resolution of Σ-Δ ADC is depends on Σ-Δmodulator; the power and area of the Σ-Δ ADC depends on the decimation filter. Thisresearch shot the power to the key points, and to optimize the area as well.The low power decimation filter in this research is for specific applications. TheΣ-Δ ADC in this research is mainly used for measurement situation whose bandwidthis smaller than15Hz. The oversampling frequency is19.2kHz to realize the24bitsresolution measurement, and the effective number of bits is18bits. For thisapplication, the system norms of the decimation filter are passband attenuation is lessthan0.01dB, the stopband aliasing less than100dB. The decimation filter composesthree parts. The CIC filter whose decimation order and factor is4and320,respectively. The CIC compensate filter and halfband filter to realize2-folddecimation filter. However, in the design of low power decimation filter, the4orderCIC whose decimation factor is320should be divided to two4order CIC filters,whose decimation factor are5and64, respectively. This division will not damage theperformance of the filters as the compensate filter has a margin for this change. Inorder to optimize the power of the decimation filter, the first idea to optimize thepower is to decrease the elements works in high frequency. As the CIC filter works inhigh frequency, algorithm is taken to optimize the elements working in highfrequency to reduce the power. In the points of circuit implementation, in connection with the design of synchronization circuit, this research used clock gate to replace theenable signal and used the logic optimization to reduce the non-essential toggle toreduce the power.In order to verification the low power methodology, this research compares thepower assumption of the regular design with the low power design. Based on thesuccessfully design of regular decimation filter, the low power decimation filter takenthe same design flow. Which from system verification by Matlab, RTL simulation byModelsim, FPGA board verification, and taken the tools released by Synopsys. It isproved that the decimation filter used low power methodology has power and areadecreased50%and25%, respectively. And the effective number of bits of the Σ-ΔADC is19.8bits.