A Low-Power And Small-Area Digital Decimation Filter Of Sigma-Delta ADC

Sigma-Delta ADC are widely used in various communication fields due to their high-resolution characteristics.It is composed of Sigma-Delta modulator,decimation filters and digital interfaces.The digital decimation filter is the main part of the chip area and power consumption of theΣ-ΔADC.In order to meet the development trend of portable and power-saving devices in recent years,and solve the complex digital circuits and high-power consumption of digital decimation filters,this paper proposes and designs a digital decimation filter,which is composed of CIC filters,low complexity compensation filter and the two-stage polyphase IIR filter cascade.It completes decimation and high-performance low-pass filtering.It has the characteristics of approximate linear phase,low power and small area.Firstly,according to the detailed analysis of the multi-stage system,approximate linear phase,low power consumption and small area of the digital decimation filter in theΣ-ΔADC,the overall architecture of the decimation filter is implemented.Each level filters are separately analyzed and design.A 5-stage CIC filter is used to complete the primary filter and 32 times decimation,in order to reduce the frequency and power of the subsequent filter.A second-order FIR compensation filter is designed to reduce the passband attenuation of the CIC and meet the design requirements of low passband ripple.The two-stage polyphase IIR filter performs 4times decimation,and completes the filtering of high stopband gain,narrow transition bandwidth and low passband ripple.The order of polyphase IIR filter is extremely low,and saves 83%multiplier than the two-stage half-band filter.Simulink modeling and simulation is completed to ensure correctness of filter order.Secondly,the circuit and RTL designs of low power and low area of filters and digital interfaces are completed.For the quantized word length,power and area of CIC filter,a non-recursive and recursive cascade structure is proposed,which has smaller area and power than single structure.For the structure of the second-order FIR filter,an extremely low-complexity circuit is designed.For the quantization noise analysis and CSD encoding multipliers of two-stage polyphase IIR filters,an all-pass filter circuit with low quantization noise and low complexity is designed.TheΣ-ΔADC interface composed of SPI byte transmission module and command control module is designed,to transmit data between external master and internal registers.Finally,the RTL-level verification platform and interface of the digital filter is designed and simulated.Based on the TSMC 0.18μm process,the gate-level netlist and digital layout is designed through logic synthesis,formal verification,static timing analysis,placement,routing and physical verification.The layout area of the digital decimation filter is 0.41 mm~2,and the power consumption is 0.136 m W.Compared with other literatures,the area is reduced by 55%and the power consumption of the filter is reduced by 92%.