Multiple Antenna Qam System Research And Implementation Of Non-ideal Factors Correction

Quadrature amplitude modulation (QAM) is one kind of high band efficiency, noise immunity modulation technology. Its modulation and demodulation system is simple. For these advantages, QAM is widely used in digital broadcasting and broadband access communication systems. However, QAM system is vulnerable to the interference of a variety of imperfect factors, leading to a sharp decline in system performance. The application of multi-antenna technology can improve the anti-jamming capability, band efficiency and link reliability of wireless communication systems. Multi-antenna QAM system can get both advantages by combining these two technologies.The main work of this dissertation is to discuss the multi-antenna QAM system with two common imperfect factors, and the correction algorithms of these imperfect factors and its implementations method. They are organized as follows.1. The architecture model of multi-antenna QAM system and the simulations of its performances (BER, constellation) are given and compared with the corrected system.2. The structural models of multi-antenna QAM system with amplitude and phase errors and phase noise are given in specific engineering background. Simulations of system performance (BER, constellation), in imperfect circumstances compared with the ideal situation are given.3. The methods for correcting the amplitude and phase errors and phase noise based on the LMS algorithm are given respectively. The simulations of the correction algorithms’performance (BER, constellation) manifest their high performance. After correction, the error rate dropped significantly, the constellation becomes legible.4. Combined with FP-DLMS algorithm, a high-speed architecture of LMS algorithm, the simulations of fixed-point correction algorithms’performance are given based on Simulink platform. It can be used for FPGA implementation. At the same time, the comparisons between fixed-point and floating-point correction algorithms’ performance is provided to illustrate that the loss of correction algorithms’performance caused by finite word length can be ignored.5. Based on Simulink fixed-point model, the FPGA implementation that is described by Verilog HDL, a hardware description language, is provided. Performance of FPGA implementation is given based on Simulink-Modelsim co-simulation. It is as good as the Simulink fixed-point model.