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Design Of FPGA-based SATA3.0 Host Controller

Posted on:2017-01-11Degree:MasterType:Thesis
Country:ChinaCandidate:Z LiuFull Text:PDF
GTID:2308330503981143Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Serial ATA(SATA) is a high speed serial bus,using the point to point transmission mode, with support hot plug, error correction capability, high transmission speed. The transmission speed of SATA1.0 is 150 MB/s, the transmission speed of SATA2.0 is 300 MB/s, the latest generation SATA3.0 ‘s transmission speed up to 600 MB/s and the SATA4.0 bus being studied is expected to reach 1.2 GB/s. Compared to the Parallel ATA(PATA) interface, the SATA interface uses two differential linesto send and receive data, which effectively overcome the crosstalk phenomenon of parallel data in the process of high speed transmission.Given the various advantages and prospects of SATA bus technology, we propose a design method of FPGA-based SATA3.0 host controller.In this paper the SATA3.0 protocolis analyzed in detail.The protocolis divided into physical layer, link layer, transport layer and application layer, and the structure and function of each layer arediscussed. Firstly, we use the Xilinx’s FPGA integrated Gigabit serial data transceiveras the hardware and design the software program based on Verilog HDL language to implement the physical layer protocol. The simulation results obtained by the tools of Modelsim show that the physical layer module can send and receive the serial data of 6 Gbps, While completing the data of serial and parallel conversion. Secondly, the linklayer protocol program is designed based on Verilog HDL language. The CRC module, scrambler module and descrambler module are designed and simulated. The simulation results by Modelsim shows that the data is processed at the speed of 600 MB/s and CRC verification, scrambler, descrambler and flow control are implemented. Finally, the transport layer protocol program is designed by Verilog HDL language. The simulation results show that the data encapsulation and resolution are achieved successfully.By the design of the physical layer, link layer and transport layer of the SATA3.0 protocol, the FPGA-based SATA3.0 host controller is completed, the host controller can communicate with SATA3.0 hard disk withthe speed of 6 Gbps and the data accuracy is ensured in the process of transmission.
Keywords/Search Tags:SATA3.0 protocol, Verilog HDL, GTX, FPGA
PDF Full Text Request
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