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Implementation Of EtherCAT Master Based On FPGA And High-performance Motion Control

Posted on:2021-05-04Degree:MasterType:Thesis
Country:ChinaCandidate:H Z ShiFull Text:PDF
GTID:2428330611498244Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
With the maturity and development of Ethernet-type transmission technology in industrial control and other related fields,various types of fieldbus technology have been widely used.The most typical one is the Ether CAT bus,which relies on high transmission speed,high transmission accuracy,wide applicability,flexible topology and other characteristics,widely used in various control fields.However,the traditional Ether CAT soft master station unable to meet the increasing demand for real-time performance in the control field,therefore,the Ether CAT hard master station based on the hardware operation platform appeared and has great application significance in improving the operation performance of the relevant control system.Porting the designed Ether CAT protocol stack to the relevant embedded hardware operation platform to reduce transmission delay and time jitter has gradually become a research trend.Based on the theoretical knowledge of Ether CAT and the operating mechanisms of the two open source master stations Igh and soem,this article designs a hardware operating platform with FPGA,PHY and network interface as core operating modules.Used XC7A100T-2FGG484 type FPGA chip,and used the programming language Verilog to logically develop the Ether CAT master protocol stack.The model used by the PHY chip is KSZ9031 RNX,which together with the network interface realizes the transmission and reception of Ether CAT data frames.On the basis of the completion of the hardware design,the construction and design work of the Ether CAT hard master protocol stack began.The main design content is as follows: related operations such as configuration processing of Ether CAT type data frames to realize the sending mechanism and receiving mechanism,determine the topological connection structure between the slave devices,the synchronization between the distributed clocks,the program composition of the master protocol stack,the module structure,the operating process,and the state transition.Finally,the Delta servo motor is used as the test object,and the relevant test operation is performed on the developed Ether CAT hard master station according to the running state of the servo moto.The final test results show that the Ether CAT hard master station can run normally and the prefetch goal is achieved.
Keywords/Search Tags:EtherCAT protocol stack, FPGA, master, Verilog
PDF Full Text Request
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