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Research And Fpga Design Of Reed-Solomon Decoding Algorithm

Posted on:2016-02-22Degree:MasterType:Thesis
Country:ChinaCandidate:Y F ZhuFull Text:PDF
GTID:2308330503976923Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Due to its excellent performance and the feature to correct continuous burst errors, Reed-Solomon codes (RS codes) are widely applied in DVD, CD, digital TV, digital image, digital audio, deep space exploration, DVB, digital communication system, DAB and other engineering fields. The JPEG2000 wireless transmission standard (JPWL) also provides error protection to image Main Header, Tile Header and other key information through RS codes. So the study of hardware implementation of RS decoding is very influential.As is the most common algorithm of RS decoding, the BM decoding algorithm and its each improved version are introduced firstly. Then the circuit diagrams and hardware complexity are analyzed. Regarding to the code type of RS(255,239), the riBM algorithm with a shorter critical path and a standard circuit structure is simulated in C++ to verify the correctness. The step-by-step decoding algorithm based on the feature of syndrome matrix and its each improved veision are also studied and a circuit structure of computing a determinant is designed.Using some digital circuit design methods such as state transition diagram and dependency graph, all kinds of finite field arithmetic units, a RS encoder, a RS decoder based on riBM algorithm and other modules which can be used in the RS decoder are designed. All modules in the RS decoder work in a pipelined manner so that codes can be entered into the decoder continuously.Then, based on the Spartan-6 device platform and the ISE software suite, Verilog HDL description, synthesis, placement&routing and static timing analysis are completed in ISE, function simulation and timing simulation are completed in iSim and position constraint is completed in PlanAhead. The final timing reports show that the maximum clock frequency of the RS encoder is 276 MHz and the maximum clock frequency of the RS decoder is 201 MHz.Finally, based on the study above, a JPWL decoding framework which meets the requirement of decoding continuously is proposed. And a code type scheme which makes the design of multi-mode RS codec the most simple is proposed under the premise of not increasing the resource usage.
Keywords/Search Tags:RS codes, BM Algorithm, FPGA, JPWL
PDF Full Text Request
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