Rs Code Encoding And Decoding, And Its Rapid Implementation

We all know reliablity and velocity are always conflict. If transmitting messages quickly,then it will short the time of transmitting a codeword ,narrow the waveform and less the power.So the probablity of arising errors will increase when encounterring noise and interference ,and the speed of transmitting messages will slow down.How to solve the conflict is the key problem in designing a communiction system. This paper gives a aborative researching of not only the widely used codes such as BCH codes and cyclic codes , but also computer simulation of the decoding or coding of RS codes.In this paper the known decoding procedures for Reed- Solomon(RS) codes are modified to obtain a repetitive and recursive decoding technique which is suitable for FPGAICPLD based on VHDL implementation and pipelining.It is show that this RS systems has the potential advantage of acheving a high decoding speed throngh parallel-pipeline processing.It can correct both random and burst errors over a communication channel.So it improve the problem in a suitable way. At the same time it gives the flow of designing a common Programmed Logic Device.In the end the most widely used codes such as convolutinal codes and Turbo codes are also introduced.