The Research And Implementation Of LDPC Codes Decoder Based On FPGA

The communication system requires high quality and efficiency. Thus, the channel coding as a significant part of digital communication draws a lot of attention. In 1960s, the low density parity check (LDPC) proposed by Gallager was proven to be an excellent channel coding. Its powerful performance approaches to the Shannon limit, the LDPC has a good prospect in information transmission research. It has been applied in many areas such as optic communication, video technology, etc. Recently, the hardware implementation of LDPC decoder has been one of the most popular topics in academy.In this paper, the LDPC codes are briefly introduced. Furthermore, Various of constructing methods of LDPC are presented. The properties of LDPC are also analyzed through different code styles and code length. In this paper, various LDPC decoding algorithms are discussed. After the analysis and comparison of the performance and complexity of various implementations simulated by MATLAB, the LLR BP decoding algorithm is chosen in this paper.After that, a quantization issue of the belief propagation (BP) algorithm for the quasi-cycle low-density parity code (QC-LDPC) of 802.16e standard under the additive white Gaussian noise (AWGN) channel are studied in this paper. We consider the quantization problem of input signal and mid-variables from the following three aspects:the variables range, bits and methods of the quantization and obtain some results. In the end, based on these simulation and data, an innovative and efficient scheme of quantization is proposed in this paper.Based on the research work and simulation results above, we developed a decoder for QC-LDPC codes of 802.16e standard which is implemented by a FPGA. We developed the RTL level Verilog code then do simulation, synthesis and timing analysis on Quartus Ⅱ 9.0 platform.