Design Of VCO And PFD/CP In Frequency Synthesizer For WSN

Wireless sensor network (WSN) integrats three technologies of sensors, micro-electromechanical systems and network communication. It is the current focus and multi-disciplinary cross research hotpot area around the world. Wireless sensor chip plays an important role in the formation and development of wireless networks, and as the key modules of RF transceiver chip, the frequency synthesizer need to provide the mixer with accurate and stable local oscillator signal.The main work of this thesis is to design the module of VCO, PFD and CP in frequency synthesizer for WSN. The whole system is based on the low supply voltage of 1V with the process of TSMC 0.18-μm RF-CMOS. The VCO is based on inductor-capacitor structure, and the cross-coupled PMOS transistors provided negative resistor pair, NMOS transistor provide the source of tail current. Switched capacitor array is used to extend the frequency range, technologies of second harmonic filter and large capacitor filter are introduced to improve the phase noise, switching currents source technology is used to save the power, and output buffer with two stage of common-source is used to drive the output signal. Final test results of VCO shows:chip area is about 0.86mm× 0.73mm= 0.63mm2, core power is around 2.7-4.1mW, output buffer stage power is around 5.7-6.1mW, the output frequency of the oscillation is around 4.66～ 6.78GHz with 37% tuning range, the phase noise is about -94～-108dBc/Hz@ 1MHz and-104--124dBc/Hz @ 3.5MHz. The test results meet the design requirements. The PFD is based on the transmission gate structure of dynamic D flip-flop with improved NAND gate structure and optimized inverter and transmission gate device. The CP is based on the structure with combined of error operational amplifier and units gain operational amplifier, and it contains optimized switching and current mirror circuit and the improved folded cascode operational amplifier. A variety of layout design improvement technology is introduced to the PFD/CP, the entire layout area is about 0.38mm* 0.18mm=0.07mm2. The post-simulation results are as follows:with reference clock frequency of 20 MHZ, PFD achieved the correct logic function without dead zone, and the phase range is about (1.94 π-1.94 π); The working current of CP is 50μA, and the charge and discharge current mismatch is less than 0.01% at output voltage range of 0.1-0.9V; the variation of CP output voltage during each of the 20 reference signal cycle is less than 0.002mV when the PFD input the same frequency and phase signal. PFD/CP total power consumption is less than 0.5 mW. The post-simulation results meet the requirements.The design of the VCO, PFD/CP with low voltage and low power consumption characteristics in this thesis meets the requirements of WSN system. It also has certain reference significance to the other chip design of wireless application.