The Design Of 1.6 GHz Low Phase Noise LC Voltage Controlled Oscillator With 0.18μm CMOS Technology

With the development of the wireless communication in recent years, the demand of lower power, higher frequency, smaller size and lower cost has been great increased. As an important block of radio frequency transceiver system, the voltage controlled oscillator (VCO) had faced the challenge of improving the power, the phase noise, and the frequency. The CMOS technology has been the main technology in the world for its low power and low cost. Thus, it is important to research and design a VCO with low power and low phase noise by CMOS technology. This paper introduces the character of CMOS components, the essential theory of VCO and the mechanism of the phase noise. The general negative conductance cross-coupled CMOS LC VCO is presented. Some important design and tradeoff strategy among the parameters of VCO are given. By analyzing the symmetry of the output wave, a method to improving the symmetry of the edge of ascend and descend was presented, which reducing the phase noise for upwards of 10 dBc/Hz. Furthermore, the paper introduces the use of switch cap array and the influence to the phase noise. A tradeoff is given to solve this problem. The quality factor of the planar spiral inductor has an important influence to the amplitude and phase noise of VCO. The noise of the other CMOS component can directly affect the phase noise. Both are discussed in detail in this paper. Some tradeoffs among them are given. A VCO with TSMC 0.18μm RF CMOS technology is presented in the final part. The frequency is 1.6GHz, with the variety frequency from 1.60GHz to 1.66GHz. The amplitude from peak to peak is 500 mV. The phase noise at 100 kHz offset is –106.9dBc/Hz. The power consumption of the core is 5mW with 1.8V power supply. The FOM is –184dBc/Hz. The VCO is applicable to IEEE 802.11b/g.