Design Of Low-Voltage VCO With Automatic Frequency Calibration

Voltage Controlled Oscillator(VCO)is a critical block in the Phased Locked Loop(PLL).Its performance,such as power consumption,driving ability,noise quality,has a profound impact on the whole performance of the system.Reducing the power supply voltage is the main measure in low power design of VCO,which has become the research focus so far.In order to realize a high-performance PLL system in GPS RF receiver,the thesis designs a quadrature voltage controlled oscillator(QVCO)in low power supply.The novel structure reduces the power consumption of the QVCO and system simultaneously,and the noise performance and practicability get further optimized.The thesis investigates and researches the realization of VCO in typical voltage,the challenge of low supply voltage as well as its solution firstly.Taken the whole power consumption of the receiver into consideration,dual core QVCO is utilized in the design to provide four local oscillator signals for the mixer.An active circuit,which combines the phase coupling circuit in the dual core of oscillator and the peak detection circuit in auto-detection bias block together,is proposed to reduce the power consumption and optimize the noise performance,moreover,the efficiency get improved further by the anti-injection current.The automatic detection and classification bias method are adopted to settle the problem that the low power consumption and rapid start-up of QVCO are difficult to be taken into account simultaneously.The proposed QVCO utilizes high bias voltage to start up at the beginning,then it will switch to low bias voltage condition to reduce the power consumption when start-up state is auto-detected.Meanwhile,hierarchical control of bias reducing degree is used to maintain the consistency of swing in broadband.In addition,the automatic frequency calibration(AFC)module is adopted to improve the practicability of the circuit.This thesis designs a low power and automatic frequency calibration QVCO for PLL system in GPS RF receiver using TSMC 0.13?m CMOS process,and the designed QVCO is verified by post-simulation and tapeout.The post simulation results show that,under the supply voltage of 0.7V,the QVCO acquires the performances of start-up time less than 150ns,differential output swing up to 0.9V,the output frequency range reaching 1.3GHz-1.8GHz,the phase noise less than-120dBc/Hz@1 MHz and the power dissipation only 1.4mW.The test results of the receiver display that the PLL can be locked and provide accurate and stable local oscillator signals,the locking time is about 40?s when the target frequency is 1.575GHz,the sensitivity of the receiver is up to-90dB with only 7mW power dissipation.