Design And Implementation Of AES Algorithm Based On FPGA

According to requirement of modern network information security, this paper based on the full study of AES algorithm, the realization of AES algorithm on FPGA were studied, proposing a design scheme of AES encryption and decryption algorithm,the AES encryption /decryption module and serial communication module are studied systematically with hardware description language VHDL(very integrated circuit hardware description language).This subject designs the AES encryption/decryption module comprises of key expansion, control and storage, encryption round transformation and decryption round transformation sub function modules, AES encryption and decryption functions can be implemented in the AES ncryption /decryption module, encryption or decryption functions are chosen by control signal, the key expansion module and the control and storage module are shared by the encryption module and decryption module. In the AES algorithm, the implementation of the optimization method is adopted in the SubBytes、Shift Rows and MixColumns, The SubBytes transformation is implemented using a look-up table, to avoid Multiple exclusive or operation in the finite field GF(28) and complicated matrix inverse; 4 byte processing mode become single byte processing in Shift Rows of the algorithm, through rearrange the 16 bytes(128 bits)to complete the operations with different displacement of 4 bytes of each line in Shift Rows; Using the shift and exclusive or operation to realize multiply by {02}(namely x) operation in the finite field GF(28), By using multiple times by {02} and method for adding intermediate results to complete the operation which multiply by the number of other. Through the realization of the above optimization, makes the design of the AES encryption /decryption system takes less hardware resources, low power consumption, meets most of the needs of the actual application.The subject make timing simulation test in the Quartus II software for each sub module of AES encryption /decryption module and the AES encryption /decryption module as a whole, the each sub module of AES encryption /decryption module meetthe design requirements by time sequence simulation test, and AES encryption/decryption module can complete the encryption and decryption functions to input data.Finally, useing the programming language VB(Visual Basic) in Visual Basic 6.0programming environment to write the PC program, through the RS232 serial port to send and receive the encryption or decryption data, the AES encryption /decryption system has been validate in EP4CE15F17C8 N which is cyclone IV E series of FPGA device.