| How to improve the CPU speed is currently a hot topic. Currently one way to accelerate is the CPU configured FPGA, which selects the programs which can speed up run on FPGA to reduce calculation of the CPU, then, improves the whole operation speed. In order to reduce the difficulty of exploiting accelerated application, the research of C-to-VHDL compiler has become a hot spot of the academic research.This thesis chooses LLVM, which is a powerful, good performance and convenient development framework, to design and implement C-to-VHDL compiler. First, detailed introduces LLVM compilation system, and analyzes the middle code, integration libraries, tools and compile process, designs a back-end code generator. This thesis analyzes the difference between VHDL and C, gives one design of IF structure to VHDL, realizes the automatic conversion of IF to VHDL, and establishes a foundation for the extension project. Then, the thesis studies the pipelining technology of FPGA, and has leading significance to the further accelerating design of FPGA. The thesis analyses the characteristics and realization methods of data pipelining, and presents three implement schemes, and compares, and emphatically introduces the realization of a division based time. This thesis also has studied the problem, how to select the optimal clock beats under the interactions between the optimization functions of ISE and pipelining. At the same time, makes the research on the optimal clock under the restriction of pipelining. Finally, makes the C code as input data, using the method of language transformation and pipelining technology introduced in this thesis to realize C code to VHDL code conversion and two pipelining ways (the pipelining based instruction number and the pipelining based time). Experiments have proved that this method can effectively achieve the automatic conversion of IF structure to VHDL code, and ensure the correctness of the design of pipelining. |
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