Hardware Design And Implementation Of AES Algorithm Based On FPGA

This paper is based on the analysis and research of the AES algorithm and the implementation of the algorithm on the FPGA,aiming at how to protect information effectively in FPGA,how to save resources effectively in the algorithm and how to improve the efficiency of implementation,this paper puts forward a hardware design scheme of AES algorithm based on FPGA,and the hardware design of the whole AES algorithm is described by using the hardware description language of Very-High-Speed Integrated Circuit Hardware Description Language.Finally,the test simulation and analysis are performed.In this paper,a compromise design is made on the comprehensive consideration of resource use and realization efficiency,which can not only guarantee certain efficiency but also reduce resource consumption effectively.This design mainly includes SubBytes.ShiftRows and MixColumns part,wheel key adding part and internal control module,the designed to support 128-bit data encryption and decryption.The SubBytes is implemented using a look-up table of the finite field GF(2~8)which avoids the complex inversion operation and reduces the consumption of resources.The ShifRowst and MixColumns part are implemented by mixed design.First of all,the complex multiplication operations in the confusion of forward and reverse columns are realized by defining Xtime()operation.Xtime()operation is compared with 8 digit highs.Then the shift and xor operation are performed according to the conditions to realize the multiplication of finite field GF(2~8)x,x~2and x~3operation.the ShifRowst and MixColumns are implemented by hybrid design,and the original two separate transformation modules are implemented by an independent module to achieve their respective functions.The key extension is to calculate all the keys and store them,then encryption or decrypt each round of the key output according to the internal control unit of control,and to SubBytes of the wheel transform provide for the key extension to use,thus reducing the cost of resources.This paper designs the AES algorithm hardware circuit system is through the input control signal to realize encryption and decryption function,when the input control signal is high,the encryption function is realized,the decryption function is realized when the input control signal is low.First of all,by EP3SE80F1152C2 FPGA devices of Stratix series is test simulation for various parts then the time series simulation and performance analysis of the whole hardware design system are carried out.The frequency of the design can be reach to 320MHz and throughput can reach2.048 Gbps,using only 6.970K ALUTs.The experiments of this design show that the high data processing speed and low resource space are achieved at low working frequency,which can protect the information security.