Design Of A High Sampling-Rate FIR Digital Filter Based On FPGA With VHDL

VHDL is considered as a core of digital system design and a key technique of implement digital systems design. Along with a very fast speed develop of PLD in speed and integration degree, increasing DSP implement with PLD. FIR digital filter often apply to dispel high frequency and restrain noises for originality stylebook data in DSP. Require of DSP in real time and fast speed is at a high pitch. This paper is arranged around the apply of VHDL in digital system design. We analyze the way of digital system design traditionary and using VHDL, and introduce the development of EDA the characteristic of VHDL and FLEX 1 OK. Pipelining design of FIR filters in digital algorithm design and implementation is described based on 4-input look-up table and pipelining design in FPGA's.The algorithm decomposing based on the pipelining technique in the work can be used in other circumstances where high speed algorithms are needed.The detailed contents of the paper are as following:In chapter 1: The detailed contents of the paper and the design of project are introduced.In chapter 2: We analyze the way of digital system design traditionary and using VHDL, and introduce the development of EDA.In chapter 3: We introduce the characteristic of VHDL , and EDA design flow with VHDL.In chapter 4: We analyze the advantage using PLD in system design and the characteristic of FLEX 1 OK.In chapter 5:It is the main section of the paper.With the method of top_down, a FIR filter architecture is implemented with pipelining design. The design is efficient and can satisfy the demand for high sampling rate. Look-up table and pipelining design are use to improve the speed of FIR filters. The particular process of implementation depictioned, and gived out the result of simulation.