High Reliability Sram Design With 6T Cell

With the development of micro-electronic technology, the integrate-circuit including memory chip has shown the developing trend toward large capacity, fast speed and low power. The static random access memory(SRAM) also has made significant growing, and has been widely used in high speed data exchange systems including computer, communication etc. Meanwhile, the integrate-circuit has been used in more and more complex environment, like magnetic field, radiation condition etc. It needs the circuit has high reliability. So, studying high reliability SRAM is of great importance both practically and theoretically. It will help on intellectual property integrated-circuit cell library building, promoting our integrated-circuit industry and improving the overall national strength.The thesis studies and introduces the overall structure, operating principle and main memory unit of SRAM at first; analyzes the typical unit circuits and adopts 6T structure as the unit of this design according to the requirement of this project. It also introduces the Silicon-On-Insulator(SOI) technology based on manufacture and application areas. By process controlling and material selection in manufacture, it will upgrade the anti-noise ability and provide chip more reliability. Then focus on main modules and whole chip layout design of this SOI SRAM project. According to the need in aerospace application, the design makes more optimization on anti-radiation single event effect aspects. During the design and implementation of the project, this thesis not only pays great effort on high reliability and high performance of the chip, but also makes comprehensive comparison on chip size, power, design reuse and extending etc. In order to achieve the design goals well, it runs optimization and improvement maximally. This thesis summarizes how to do module and layout design, brings up some innovation and ideas about design optimization. In the final validation, generates complete drive signal and selects key path, runs comprehensive post-simulation based on three different model conditions. It also tests elector static discharge(ESD) and anti-radiation characteristic after manufacture. In the design, the address access time is 12.416 ns, the static power is 50.54μA, the dynamic power is 36.45 mA, the highest voltage for ESD is up to 3000 V, the single event upset rate is more than 37MeV·cm2/mg and the ability of total anti-radiation is over 1.5x103Gy(Si). All these data are meeting the design specification, and so make the chip design succeed at one time.With this project, a high reliability and performance SRAM is designed, an ownbrand SRAM unit library is created. These jobs lay the foundation for further research and development, and accumulate a lot of experience.