Research Of Scan Tree Design For The Reduction Of Test Time And Test Power

Design-for-Testability techniques are widely applied to facilitate the testing ofintegrated circuits and systems. Scan design is the most common method in Design-for-Testability. However, scan design, especially full scan design, has the drawbacks oflong test application time and high test power consumption. This gives rise to the hightest cost of scan designs.Scan tree architecture can effectively reduce the test time. However, mostprevious scan tree techniques are based on noncompact test pattern sets. This kind ofapproaches is not applicable to compact test set design. Moreover, most commercial testpattern generators usually provide compact test pattern sets. Therefore, it’s imperativeto propose a scan tree generation scheme for compact test sets. Despite its efficiency intest time saving, the scan tree architecture consumes excessive power during test. Yetmost existing low power techniques are not applicable to scan tree architecture. Thus, apower-aware method for scan tree design is of great value.The relationship between scan tree generation and test data is first modeled. Thismathematical model reveals the key factor in achieving low-height scan tree, andverifies that the noncompact test set based scan tree techniques are not applicable tocompact test set designs. The theoretical analysis quantitatively gives the bound of treeheight that the approximate compatibility method can achieve. Results from ourimplementation of this method support this bound.A scan tree generation method for compact test sets is proposed in this thesis.Inverse compatibility is introduced in scan tree generation. It helps to include morecompatible scan cells to construct a scan tree without incurring more fault coverage lossthan the traditional direct compatibility. Aggressive compatibility is first proposed inthis thesis. This novel compatibility can significantly improve the compatibilityrelationships between scan cells. The effectiveness of scan tree construction is thusdrastically improved. A low power scan tree technique is proposed. The test power of scan tree isoptimized by exploring the relationship between the number of transitions andnontransitions. The novel Q′-D connection style is exploited to implement the proposedscheme. This method does not introduce any hardware overhead or performancedegradation. Moreover, balancing between transitions and nontransitions always ensurea power reduction.Experimental results show that the introduction of the proposed aggressivecompatibility can reduce the scan tree height several times, compared with existingtechniques. Test time, therefore, is significantly reduced. Though this method isparticularly proposed for compact test set designs, it is effective in test time saving fornoncompact test set designs. Experimental results indicate that the Q′-D connectionscheme can effectively reduce test power of scan tree. Since the inherent Q′port ofregisters is used, zero overhead will be introduced.