Fault-Tolerant And Low-Power Coding-Decoding Design Based On Network On Chip

Through silicon vias (TSV) is used to connect different layers of 3D NoC. The chip yield decreases with the increase of the number of interconnect TSVs because of the limitation of manufacturing processes, which seriously affects the reliability and applicability of 3D NoC. In addition, power consumption has been a hot issue because of the increasing of chip complexity, excessive power consumption leads to increasing the temperature sharply, which seriously influences the reliability and performance, and increases area overhead and encapsulation cost. As to the issues of the chip yield, we have proposed a fault-tolerant scheme in this paper to ensure the communication among the vertical links when some TSVs are failed. As to the issues of power consumption, we have adopted low power encoding-decoding to reduce power consumption. The main works as follows:1. A self-adaptive bit-width reorganization scheme is proposedReorganizing the data transferred between layers according to the number of fault-free TSVs in faulty channel, the bit wide of the reorganized data equals to the number of the fault-free TSVs, and thus all the fault-free TSVs are used to transfer data between layers. The key circuit to implementing this scheme is design a special shift register with configurable shifting width, which can operate both shifting and loading in one cycle. Through this way, the operation cycle is reduced while the data is reorganizing, and the efficiency of reorganization is improved. The circuit proposed in this paper can improve the chip yield, and can reduce the latency of the fault-tolerant circuit. The proposed circuit permits (N - 1/N)% fault rate of TSVs (N presents the total number of TSV). The transmission delay of the new proposed method can be reduced by 49% at most compared with existing fault-tolerant methods.2. Design and implementation of low power encoding-decoding circuit:As to the self-transition of interconnecting wires, we divide data into 4 groups and use the coding algorithm separately to reduce power consumption significantly, adopting the idea of invert encoding and block coding. Considering that the transition algorithm does not perform so well when applied to sequential data, we use Gray code to implement associated coding according to the data format of specific NoC. As to the coupling transition between interconnecting wires, we use E/O BI coding algorithm, subdividing the steps of the algorithm and applying gated clock to make sure that there is only one module to work at the same time, so that the power consumption is reduced. Experimental results show that invert-coding can reduce power consumption by 12.1%, and E/O BI coding can reduce power consumption of NoC by 13.7%.