Research Of Fault Tolerant Scheme On Control Logic Of Network-on-Chip

As a popular scheme to connect hundreds of processing elements in modern computing platforms, Network-on-Chip can target the disadvantage from traditional bus connection, such as low extensibility, low efficiency and global synchronization requirement. However, it is inevitable that on-chip network will suffer from challenges to the reliability when feature size of integrate circuits decreases aggressively. Under this circumstance, faults occur in NoC. Faults in NoC can be classified into data path fault which damages the integrity of data and control logic fault which hinders the functions of NoC with more difficulties of fault detection and tolerance. In this dissertation, faulttolerate schemes for control logic of NoC are researched.First of all, the types, the characteristics and the causes of control logic fault have been researched. Also, the weaknesses of current fault-tolerate schemes in literature are analyzed. In this part, a more reasonable and fine-grained fault model is built where the faulty routers are not necessarily turn off but keep maximum usage of the available resources and maintain the task processed coherently on process elements.After that, two fault-tolerate schemes aiming at control logic fault are proposed, the redundant control logic based fault-tolerate scheme and the non-minimal routing based fault-tolerate scheme. By using simplified redundant modules, the former can offer limited but necessary service for packets under control logic failure and achieve even higher reliability than TMR scheme. The latter takes new aspect of using the non-minimal routing algorithm to tolerate illegal turns which are the common faulty behaviors under control logic fault. With the multi-forward option, packets which suffer from illegal turns can be eventually delivered.At last, average latency, reliability and hardware overhead are evaluated in POPNET, a cycle-accurate NoC packet behavior simulator. Results show that both of the proposed schemes can achieve more reliability in faulty NoC wirh reasonable latency and hardware overhead increase.