Coding Based Research And Design On Reliability In Network On Chip Interconnects

As technology scales toward deep submicron,. Network on Chip interconnects are becoming more and more sensitive to a variety of noise sources, so that the reliability becomes a major branch of NoC research. Coding based error control schemes are considered effective fault tolerant methods at present.This paper focuses on the research of fault tolerant schemes for data transmission on the NoC data link. The NoC routers which adopt fault tolerant schemes are implemented with Verilog HDL, simulated and synthesized by Synopsys EDA software. The performance analysis of the fault tolerant schemes are accomplished in a 4×4 2D-Mesh NoC composed by the fault tolerant routers.First, this paper discusses the main research contents of NoC communication reliability and the state of the art. On this basis, we propose the key technologies of NoC communication reliability. For transient errors, we adopt coding based hop by hop and end to end error detection and recovery scheme to design two kinds of fault tolerant routers. We also evaluate the two fault tolerant schemes in terms of fault tolerant performance, power and area overhead. Secondly, this paper presents a new coding scheme in order to solve the major source of transient errors under deep sub-micron process. The new coding scheme achieves joint crosstalk avoidance and error detection on data link. Thirdly, we improve fault tolerant routers and realize its capability of permanent error detection and location, which support dynamic routing mechanism based on network monitor proposed by our group to solve the issue of permanent errors on data links.A comprehensive fault tolerant scheme is designed in this paper, which deals with both transient and permanent errors on NoC data links. This scheme provides a reference for design of fault tolerant router, coding for reliability on NoC data link and fault tolerant NoC architecture.