Design And Implementation Of DDR3 Controller's Physical Layer Based On FPGA

With the development of technologies such as artificial intelligence,the Internet of Things,and big data,the requirements for data transmission rates have become more stringent.The transmission of high-speed data is affected by the environment,crosstalk,and differences in wiring delays,which will cause the signal quality to deteriorate.So reliable sampling of high-speed data is very challenging.In order to ensure reliable sampling during DDR3 data transmission,this paper proposes a physical layer read-write channel calibration method based on phase adjustment,wiring delay difference compensation and other means.The calibration scheme designed in this article does not require DDR3 particles to enter MPR mode to achieve read channel calibration.While ensuring the phase relationship between the sampling clock and the data,the skew between the data bits is also adjusted,which makes the data effective sampling window larger.This solution builds read and write data channels and command channels on the FPGA.First,complete the phase relationship calibration between the write data channel and the command channel in the granular write leveling mode;then set a larger write delay time to correct the same address in a row of addresses The unit continuously burst writes complete one or zero data to achieve data coverage,and finally realizes the interleaved writing of one and zero regular data in adjacent address units;then enters the read channel calibration stage,and reads back the regular number that have been written into DDR3.Determine the edge of the data unstable interval by moving the phase of the data sampling clock of the read channel,adjust the skew between the data,and then move the sampling clock to the center of the new valid window of the data.Finally,the calibration of the write data channel is performed.Write the regular number to the particle first,and then read back the data written to the particle.The law number is used as the basis for judging the phase relationship between the write channel data and the clock.Change the write delay to correct the write delay period between the CAS command and write data,adjust the write channel clock phase to find the edge of the data unstable interval,and adjust the skew between the write channel data.Move the sampling clock of the write channel to the center of the data valid window to complete the calibration of the write data channel.Through the FPGA test board of model xc7vx690tffg1761,perform the performance test of the read and write channel of the physical layer calibration scheme under three different temperature environments of high,low and normal.The read channel is under the three environmental temperatures through manual window adjustment to find the data valid window The size is greater than 380 ps,and the difference between the clock sampling edge and the center of the data valid window is only 30 ps,which proves that the read channel calibration algorithm is reliable.The test results of the write channel eye diagram under three ambient temperatures all show that the data DQ eye width is above 378 ps,which meets the DDR3 JEDEC standard,and the edge of DQS is located at the center of the data DQ eye diagram,which proves the reliability of the write channel calibration algorithm.At the same time,the burst eye pattern test was carried out at the maximum operating frequency of the particle at 933 MHz.The DQ data eye width reached 383 ps,and the DQS edge was located at the center of the DQ eye pattern,which proved that the calibration scheme is highly reliable in ensuring the transmission of DDR3 high-speed data.