The Design And Verification Of Key Modules In PCI Express Data Link Layer

The rapid development of bus technology has led the traditional parallel bus to a bottleneck in structure and performance, which leads to the merge of the third-generation PCI Express serial bus. Its high cost performance and strong flexibility has been noticed by users and researchers. As the intermediate layer between Transaction Layer and Physical Layer, Data Link Layer(DLL)’s main task is to protect the reliable transmission and integrity detection of data. There is certain value and significance in the study of PCI Express.As a part of PCI Express2.0 standard, the DLL was studied and the implementation of the DLL’s important function was designed based on FPGA. The hierarchy of PCI Express bus, as well as the domestic and foreign research status are described firstly. The basic concepts of communication mechanisms, information packets, CRC check and transmission mode are described in the dissertation. Then the features and implementation techniques of the DLL are depicted. The top-down design methodology is used to divide the DLL into modular design. The register transfer level (RTL) design of key modules, such as the receiver, transmitter, states control, power management and so on, are synthesized by the Verilog hardware language. At last, the delay in the design.is analyzed and summaied in this dissertation. In the end of the dissertation, the problems in the design and the direction of further research are pointed.Using the Modelsim software, all the modules alone and the system of all are simulated completely. The corresponding simulation results are offered. By ISE, synthesis, place and route, state timing analysis are done. The logic synthesis results at RTL are given. Based on Xilinx Virtex-7 series FPGA, the DLL serial self-loopback test is verified. The results show that the DLL of PCI Express2.0 is realized and the logic function is correct.