Design Of Main Controller With Task-Level Out-of-Order Multi-Issue In Multi-Core Systems

With the development of multi-core technology, more and more processing cores are integrated on a single chip, bringing much more powerful potential computing capacity. However, there are many processing cores being idle for a long time in most multi-core systems at runtime. Thus they do not obtain the ideal parallelism and the potential computing capacity is not taken full advantages of, resulting in a big waste of computing resources. Therefore, it is a very important research to effectively schedule the on-chip processing cores and fully exploit the parallelism.Task-level Out-of-Order(OoO) multi-issue is derived from the widely-applied instruction-level OoO multi-issue techniques in single-core systems, including the register renaming and dynamic schedule etc. In coarse-grain task pipeline, which consists of several processing cores, task-level OoO multi-issue technique is used to automatically trace data dependences among tasks and flexibly schedule the processing cores, so as to fully exploit the task-level parallelism and enhance the resource efficiency.Given above problems, this thesis does some relevant research about how to design a main controller to support the task-level OoO multi-issue in multi-core systems based on Network-on-Chip(NoC) communication architecture. The main tasks of this thesis are as follows.Firstly, this thesis deeply studies the principle and implementation of the key techniques about traditional instruction-level OoO multi-issue. Then analyze the challenges of extending them to the situation where task-level OoO multi-issue is employed. Introduce the properties of the target system and analyze the requirements to realize the task-level OoO multi-issue in the target system. Also give out the solution for the challenges and the requirements.Secondly, this thesis proposes a novel main controller design to support the task-level OoO multi-issue. The main controller adopts a two-level programming architecture, designs a task-level register renaming scheme to eliminate false data dependences, traces true dependences between tasks and registers instead of inter-task dependences, and resolves structural hazards and control hazards with a resource allocator and a branch predictor respectively. In addition, this thesis designs a novel task-level dynamic scheduler and a resource allocator, which manages all the processing cores. Also the SIMD work mode among multiple processing cores in a task is supported in this thesis.Thirdly, this thesis completes a pipelined design for a reconfigurable computing unit (RCU) and proposes a heterogeneous multi-core system based on NoC. Several experiments are finished on the system to verify the function of the main controller.Finally, according to the main influence factors of task-level OoO multi-issue technique, some applications with different properties are mapped onto the heterogeneous multi-core system in order to evaluate the performance of the system under the control of the main controller. After that, the task mapping principles are explored preliminarily.