Research On Multi-issued Dynamic Scheduling Main Controller Of Heterogeneous Multi-core Processor

With the development of processors,only relying on the single-core performance of the processor to improve the overall performance has encountered a bottleneck.The computing parallelization of multi-core processors is a hot topic of research now and in the future.How to reasonably schedule all computing units to make the system computing can be carried out in parallel,and improving the utilization of computing units will be the key to improving the computing performance of multi-core processors.Around the above problems,this article designs a dynamic task scheduling controller for heterogeneous multi-core computing systems.Through the analysis of the computing behavior of the system,it mainly realizes the functions of dynamic monitoring of the load of the computing unit,dynamic task wake-up,automatic extraction of task parallelism,out-of-order multi-issue of tasks,and safety management of task write-back.A method to reduce the times of the result data of a computing task written back to the DDR external memory is studied,which greatly saves the memory access overhead and further improves the computing performance.This article discusses the task instruction fetching,scheduling,issuing,writing back,wake-up process and the corresponding hardware circuit structure,and completed the simulation test.Simulation and testing show that in typical application scenarios,compared with the original task issue controller without dynamic scheduling function,it has realized the transition from explicitly parallel programming to task parallel automatic control,and the programming friendliness is significantly improved.In different cases the calculation performance has been improved by 11.3%-37.9% respectively.This article uses the existing heterogeneous multi-core heterogeneous computing system with the network on-chip as the communication carrier as the target platform,and conducts an in-depth study on how to make full use of the computing performance of the computing system.The main work of this article is as follows:1.In-depth analysis of the characteristics and workflow of the original multi-core computing platform,as well as the performance bottleneck when running a large scale of calculations,and aiming at the problem that the original heterogeneous multi-core computing system can only be executed in the order of pre-written program instructions,the basic principles and methods of hardware automatic extraction of parallelism between tasks and real-time dynamic task scheduling are studied,and a solution for dynamic task scheduling and task out-of-order issuing for target computing platforms is studied.2.Combined with the specific workflow of the target computing platform,the concept of tasks and the method of task division are defined,and the task dependency table is designed to record the basic attributes of tasks and the data dependencies between tasks.The task dependency table also contains additional instruction information used to control the task execution process,which together form the basis of the scheduling controller when scheduling tasks.Under this premise,a hardware design scheme of the main controller that can support real-time dynamic task scheduling and out-of-order issuing is studied.By reading the information in the task dependency table,tracking the data dependency between tasks and the computing resource consumption required by the task,monitoring the busy state of the computing unit on the target on-chip network computing platform through the status network,and determining the number of computing unit available for scheduling,so as to realize the dynamic monitoring of whether the task meets the issue conditions,and provide the basis for dynamic task scheduling and out-of-order issue.3.Completed the dynamic update-issue design of the programming configuration program for the existing target computing platform.Through the dynamic remapping of the computing node coordinates occupied by the task during scheduling,it is solved that the existing target computing platform can only statically specifying the coordinates of the calculation node during programming,so as increases the flexibility of programming.In the dynamic mapping strategy of the task,consider using the nearest neighbor algorithm to issue the task to the computing unit closest to the computing unit that generates the source data required by the task,which reduces the delay of the data transmission link between the nodes.Besides,the preparation queue method is used to prepare the computing nodes required for the successor task of the task in advance,and multiple selectable target nodes are provided,which hides the time to search for idle computing units on the system and improves the efficiency of task mapping.4.In response to the requirements of whether the result data is forcibly written back to the DDR storage area when the task calculation completed,and whether the task forms a task chain with other tasks,four task types are defined.The strategy of forming a task chain dynamically and issuing tasks as many as possible improves the utilization of computing units and reduces the times of tasks written back to and read from DDR memory,which increases calculation density,reduces memory access time consumption,and improves the computing performance of the target calculations platform.5.On the basis of dynamically forming a task chain to reduce the times of tasks written back to the DDR memory and issuing tasks as many as possible,for the task that can only be written back to the DDR memory,enable the idle node on the system as a temporary storage.It is used to store the result data of the task,which further reduces the times of the task written back to the DDR memory and read data from the DDR memory,and saves a lot of memory access time,and further improves the computing performance of the target computing system.6.In view of the possible complex data transfer relationships between tasks,such as tasks with multiple predecessor tasks or multiple successor tasks,a data security management mechanism suitable for both complex task graphs and simple task graphs is studied.7.Aiming at target computing platform,after the hardware implementation of the scheduling controller is completed,a variety of test sets are constructed to map applications with different characteristics.After the dynamic scheduling controller is used,the overall running time of the computing application and other indicators are tested.By comparing with the overall running time and other indicators of the existing target platform without a dynamic scheduling controller,the overall performance improvement effect of the system brought by the dynamic scheduling controller is obtained,and the feasibility and functional correctness of the scheduling controller are verified.