The Simulation And Implementation Of Processor Register Level For OpenRISC

The increasing function of System on a Chip(SoC),increasing design complexityand difficulty and increasingly shorter product cycle have been made processorsimulation become more and more attractive. During the design of hardware,processor simulation can be used as a handler function verification of referencemodels while in the stage of software design,it can be used as system supportplatform for software development environment which is of great significance. Inorder to promote the development of open source OpenRISC processor technologyand verify the advantages of processor simulation which based on SystemC language.In this paper based on SystemC we have simulated open-source OpenRISC processorsand OpenRISC microprocessor minimum system of the simulation are given,what’smore,we also have introduced the OpenRISC pipeline line simulation design andimplementation which may lay the foundation for further simulation and developmentof OpenRISC processors based on SystemC.The work of this paper are mainly including：Firstly, processor simulation technology and SystemC hardware simulationplatform was analyzed. Meanwhile,the functions and features of instruction set andconstruction set simulation technology in processor simulation technology,the designmethodology, simulation kernel and process features and functions of SystemChardware simulation platform were introduced in detail respectively.Secondly,the structure frame of OpenRISC1200processor core was discussed,and through the way of cutting additional unit we get minimum system which includeinteger unit,register unit and memory;the function of different levels of pipelineline,possible risk in all levels,risk conditions and the solution of every risk were alsodiscussed;Moreover,we introduced the characteristics of Cache technology whichOpenRISC adapted for matching difference between main memory and CPUperformance; besides, OpenRISC characteristics analysis and classification ofinstruction set were given.Thirdly,OpenRISC processor pipeline line simulation design is make use ofSystemC and OpenRISC processor overall design frame were given; The simulationof IF level genpc module, ID level control module and rf module, EXE leveloperandmuxes module and alu module, MA level lsu module, and WB level wbmux module were successfully realized; at the same times, the realization of Cachesimulation were also given.Finally, combining with the SystemC simulation development platform, after thethe necessary initialization work; for data hazard, Pipeline jam, flow linecomprehensive performance and data Cache function test cases were designedrespectively, and give the executed result and relevant code; theoretical analysis andexperimental results show that base on SystemC to simulate OpenRISC processor coreis available, so on the basis of it we can continue to develop and improve and use it tosupprot Software and hardware development and design which based on OpenRISC.