The Design Of Super-speed Data Acquisition System Based On FPGA And USB3.0

Data acquisition system is the most significant part of information system, and it is the foundation of digital signal processing and analysing,which is widely used in many areas such as radar, communication, remote sensing and so on. In order to meet the needs of real-time monitoring of radar, the thesis suggested a scheme of high-speed data acquisition system which is composed of high speed ADC, high performance FPGA and USB3.0(Universal Serial Bus) port. Take the FPGA as core controller of the system, realizing data collection, buffering and driving peripherals. Without the control of CPU, the hardware operation mode of data acquisition and transmission makes the system faster.Firstly, we analyze the architecture and interface of high-speed data acquisition system domestic and overseas at this stage.For the shortcomings of traditional hardware structure and interface, the research on high speed data acquisition system, which is based on FPGA and USB3.0 architecture, is necessary and of great significance. Then hardware design technology is detailed presented of the system, including FPGA, DDR2 and USB3.0 etc. The routing rules, electromagnetic compatibility and signal integrity are discussed in the paper. The overall architecture of FPGA logic system is put forward. Pipeline data processing, DDR2 ping-pong buffering mechanism and driving mode of FX3 are detailed introduced in the article. Afterward the paper presents the designing process of FX3 firmware, driver and software.Finally an experiment is conducted in vaious channels and multi-mode condition, acquiring and analysising the data, in the laboratory environment.The result shows that there is no cross talking and data error phenomenon when in large number transfer or continue mode, and the data transmission speed can be up to 255.28 MByte/s.The scheme of FPGA and USB3.0 is adopted in the super speed data acquisition system, which ensures high speed and flexibility of the system.