Research On Design And Implementation Technology Of 512Kbit Anti-fuse OTP Memory

As mankind enters the era of space-flight, it becomes more and more important to store the data stablely and correctly in the high radiation environment of space. With its stability, reliability, strong anti-interference ability and excellent anti-radiation performance, anti-fuse OTP ROM is widely used in the fields of strict requirements, such as aerospace, aviation and military. So far, however, in the field of anti-fuse OTP ROM, we still have not implemented self-designed products. The main purpose of this thesis is to study how to design and implement a stable and reliable anti-fuse OTP ROM with integration density of 512 Kbit. The design process includes storage unit, ESD protection, redundant testing circuit, as well as programming and read-out circuit design and simulation. Then design the layout, after tape out, chip were packaged and tested.After research of a variety of anti-fuse units of home and abroad, a new gate oxide anti-fuse compatible with commercial CMOS process was used, the 1T1 C memory cell structure was designed. The resistance after anti-fuse element breakdown has good consistency, the resistance is small. In order to facilitate the fast digital simulation of the whole circuit, the model was built and the simple simulation of the memory cell was carried out.In the design of peripheral circuit, considering the product of the chip, the ESD protection structure of the memory is designed. Then the memory array and multi-level decoding structure was designed. In order to facilitate the testing of products, the redundant testing circuit was designed, and the test of OTP ROM was realized. In the programming circuit, the two-stage charge pump circuits was designed to achieve the internal control of the high voltage, so that the error programming of non-selected units can be avoided. Then the sense amplifier and the two-stage DICE latch were designed, So that the data can be read out stablely and correctly. The function modules of redundant testing circuit, programming and reading are simulated and verified by SPECTRE simulation tool. In order to quickly realize the function of the whole circuit verification, the circuit module was replaced by the Verilog code. Then the AMS simulation tool was used to implement the rapid functional verification of the whole circuit. After that, in order to ensure the accuracy of the circuit function, the whole circuit was simulated with the Finesim simulation tool. Then completed the final circuit design.After the completion of the circuit design, the layout design and implementation are carried out. The Place and Route of the layout, and the Radiation Hardening by Design used in the layout are introduced. After the completion of the layout, the layout was verified by DRC and LVS by using Calibre.After that, the parasitic parameter extraction and post simulation were carried out. Then, GDSII file was exported and we sent it to the foundry to tape out.Finally, the actual chip was packaged and tested. The test results showed that the chip’s read and write functions were correct, and storage capacity met the design index.