Design Of Anti-Fuse Prom

Once programmed, cell of one time programmable (OTP) memory is permanently break down or fused. The program condition (such as high voltage) doesn't exist when memory works normally, as a result, it raises reliability of OTP memory. It supports custom program for one time, but the area which is not programmed can be used to replace or refresh pre-existing data through certain data management arithmetic, so it develops flexibility of memory use. And it is cheap and easy to design, so OTP memory is very suit for some applications, such as embedded system, aerospace and secret key storage, etc.This OTP memory based on anti-fuse cell includes storage array, decoder, program and read circuits, error detect and correct circuits, power circuits and logic control module. Firstly, anti-fuse memory cell is studied, after comparing three structures of anti-fuse memory cell, single transistor structure is selected because of its'fast speed and advantage of storage capacity. Storage mechanism of anti-fuse memory cell, breakdown characteristic and resistor characteristic after being break down are studied, and storage array is designed. Then periphery circuits of anti-fuse programmable read-only memory (PROM) are analyzed and designed. The multidimensional decoders adapt to memory array arrangement and reduce signal transmission delay. Program circuits and reading circuits is designed to write and read data. To ensure accuracy and reliability of storage data, error detect and correct circuits and redundant function are added. Low dropout regulator (LDO) is designed to provide 2.4V voltage for data reading, and STC structure is applied in this LDO to improve performance of transient response. At the end, the system is simulated by Spectre and Nanosim. The result shows that functions and performance of this anti-fuse PROM satisfy the requirements.This thesis accomplished the design of a 16k bits anti-fuse PROM memory based on normal commercial process, it can be used to store configuration data and program data for main control chip.