Design And Research Of High Capacity OTP Memory

As one time programmable memory, users can utilize the OTP memory to read the data and information which are stored freely earlier. With many advantages, such as higher reliability, strong stability and ability of radiation harden, the OTP memory is widely employed in secure key storage, embedded memory and as a trade-off between Mask-Rom and EPROM, OTP memory can function without complicate erasure mechanism and meanwhile allow users to configure the memories freely to a certain extent. They are widely used in secret key storage, embedded memory military field and aviation and aerospace where the dependability and security of the data configuration and information acquisition is of great important. Based on CMOS 0.18μm manufacturing technique, the purpose of this thesis is to design an OTP memory with a high integration density of 256 Kbits and finally tape out.With a combination of deep theoretic analysis and graphics test, a reliable and feasible OTP memory cell is proposed, which is the footstone and basic part of an entire OTP memory. By circuit analysis and simulation, the whole peripheral circuits are put forward. The work performance of the main circuits modules are described detail. The signal lines of this OTP memory with 8bit data with are 26, including 15 address signal, 3 enable control signal and 8 data in and out ports. By using the way of classifying decoding, the address decoders are able to access to the memory cells. The high programming voltage is about 7V and the two level charge pumps make sure that the high voltage can be transmit to the programming points free of losses. And the reading circuits is aimed at outputting data accurately and steadily.The layout of the high density OTP memory is realized. During the process of layout design, the main structure of the whole chip has been considered, as well as the method of global planning and placement, the planning of power and ground signals and the way to route. Except making sure the consistency of layout and schematic, the problems which could be induced in the process of manufacture are worthy of attention. After the layout design is finished, it is supposed to be verified by DRC and LVS by using Calibre. And then to make sure the basic function of the OTP memory is accurate, with the extracted parasitic parameters in the layout, The post simulation is proceed. The results of the post simulation are the most proximity data to the result of the actual test of tape-out chip.Finally the design proposed in this paper is verified to be a success one. The testing of the tape-out chip proves that the practical capacity of this OTP memory is just 256 Kbit and the working function of it is accurate.