The Hardware Design Of PCI Express Bus Analyzer

PCI Express is the third-generation and high-performance bus interface.It has faster transmission rate,higher bandwidth and more flexible connection mode than the PCI,which is the second-generation bus interface.Besides,PCI Express devices support hot swapping and they are compatible across platform.PCI Express 1.0 version supports x1 、 x4 、 x8 and x16 transmission mode.Each channel can provide 2.5Gbps bandwidth.While the bandwidth doubles with the channels’ doubling.Due to the complexity of PCI Express protocol,it is difficult to analyze it by artificial means.And using artificial means is very easy to make mistakes. Therefore, it need the specialized instrument to analyze the PCI Express protocol.This topic is based on the x1 transmission mode of PCI Express 1.0 version to design the PCI Express bus analyzer.And it combines with PCI Express protocol to conduct the study mainly from the following several aspects:(1)The data acquisition section.The data acquisition section compromises the sampling clock circuit and the data acquisition circuit.The sampling clock circuit provides the 2.5GHz sampling clock signal for the data acquisition circuit to realize5GSa/s sampling rate through the bilateral sampling principle.The data acquisition circuit adopts the way of "sampling chip acquisition circuit + FPGA acquisition circuit" to acquisite the 2.5Gbps signal of PCI Express 1.0 bus.(2)The data storage section.The data storage section uses the DDR2 SDRAM memory particles to store the PCI Express 1.0 bus signal across clock domains with the IP core in FPGA.And the storage depth is 256 MB.(3)The protocol triggering section.The protocol triggering section compromises the signal extraction module and the trigger module.These two modules decode and trig on PCI Express 1.0 bus signal respectively according to PCI Express data packet format.Signal extraction module decodes the acquisition data and determines that the data is in which field of the packet and the specific location of this field.Trigger module triggers the PCI Express 1.0 bus signal from physical layer to transaction layer.It compares the decoding data with the specific trigger word.Trigger types include the frame starting triggering,the TLP header type triggering,the TLP transaction types triggering,the DLLP transaction types triggering,the data poisoning triggering,the frameending triggering and the PLP triggering.This topic completed the PCI Express Bus Analyzer to achieve the 5GSa/s sampling rate and 256 MB storage depth,it can can accurately acquisite and store the PCI Express bus signal of 1.0 version and capture the data in accordance with a variety of trigger mode.