Research And Realization On Reconfigurable Digital Receiver

In the radar and communication systems and other electronic systems, facing increasingly intricacy electromagnetic circumstance, a general hardware and software platform is urgently needed to solve the interoperability and compatibility between different systems in information transmission field, as well as to realize the optimal reception of multi-band, multi-mode signal. Reconfigurable digital receiver appeared on this background, which can receive the signal which has different frequency and band by using the tunable hardware and the programmable software. Reconfigurable digital receiver is versatile, real-time adjustability and extensibility, etc.Based on the research on related literature about reconfigurable digital receivers at home and abroad in recently years, this thesis mainly studies a kind of reconfigurable receiver structure based on twice sampling. The basic principle and the performance of reconfigurable receiver has been analyzed and a concrete scheme of the receiver has been presented in consideration of the difficulty to implement in domestic device level, and actual simulation and design of each module also has been done.The primary work of this thesis includes:1. The proposed reconfigurable receiver scheme is analyzed, advantages of the reconfigurable digital receiver which is based on the ideal of twice sampling in the field of reconfigurable receiver is explained, and reason to use this structure is also explained. And the principle of the structure and the feasibility of this scheme is analyzed.2. The classic reconfigurable digital receiver structure was analyzed, advantages and disadvantages of every reconfigurable receiver system are studied, and a practical scheme of reconfigurable digital receiver is put forward, and the theoretical analysis to the proposed solutions is also made.3. Aiming at reconfigurable digital receiver scheme, noise sources which influence SNR of receiver systems are analyzed, and main noise source—clock jitter is modeled and the SNR is compensated.4. The technical indicators of receiver system is put forward, and the reason to select main devices is explained, which include ADC, FPGA, clock chip and power supply chip.5. The digital front-end is designed, and software and hardware codes for the digital module are written. The simulation to every module of the digital front-end is made on the software and hardware simulation platform.6. The whole receiver system is built by using the selected ADC, FPGA and clock chip, and then the digital front-end had been realized. Results show that the design of the reconfigurable digital receiver satisfies the requirement of design.